1. Field the Invention
The present invention relates to a power converter, and more specifically, relates to a switching controller of the power converter.
2. Description of the Related Art
A switching controller of a power converter is utilized to regulate an output voltage from an unregulated input voltage. In conventional power converters, a current-sense resistor is generally connected in series with a power switch to generate a voltage representative of a switching current flowing through the power switch. However, this current-sense resistor causes inevitable power consumption, which reduces the efficiency of the power converter under light-load conditions.
FIG. 1 shows a conventional power converter. The power converter comprises a switching controller 50, a transistor 20, a transformer 10, diodes 11 and 21, capacitors 12 and 22 and a secondary feedback circuit 16. The switching controller 50 comprises a PWM circuit 30 (PWM) and comparators 31 and 32. The transistor 20 is a high-voltage device, which is, for example, the power switch as aforementioned.
The transformer 10 includes a primary winding NP, an auxiliary winding NA and a secondary winding NS. A first terminal of the primary winding NP is supplied with an input voltage VIN. A second terminal of the primary winding NP is connected to a drain of the transistor 20. A drain voltage VD, which is a high-voltage signal, is obtained at a joint of the second terminal of the primary winding NP and the drain of the transistor 20. A current-sense resistor 25 is connected between a source of the transistor 20 and a primary ground reference. A second terminal of the secondary winding NS is connected to an anode of the diode 11. A first terminal of the secondary winding NS is connected to a secondary ground reference. The capacitor 12 is connected between a cathode of the diode 11 and the first terminal of the secondary winding NS. The output voltage VO is obtained across the capacitor 12.
A first terminal of the auxiliary winding NA is connected to the primary ground reference. A second terminal of the auxiliary winding NA is connected to an anode of the diode 21. The capacitor 22 is connected between a cathode of the diode 21 and the primary ground reference. A supply voltage VCC is obtained across the capacitor 22 to power the switching controller 50.
The secondary feedback circuit 16 comprises a resistor 13, a zener diode 14, and an opto-coupler 15. A first terminal of the resistor 13 receives the output voltage VO. A second terminal of the resistor 13 is connected to a cathode of the zener diode 14. An anode of the zener diode 14 is connected to an input of the opto-coupler 15. A first terminal of a resistor 33 receives the supply voltage VCC. A second terminal of the resistor 33 is connected to an output of the opto-coupler 15. Therefore, the output of the opto-coupler 1$ is pulled high by the resistor 33. A feedback signal VFB is generated at the output of the opto-coupler 15 in response to the output voltage VO of the power converter.
The current-sense resistor 25 converts a switching current IP flowing through the transistor 20 into a current-sense signal VCS. The current-sense signal VCS and a current-limit threshold VLMT are respectively supplied to a negative terminal and a positive terminal of the comparator 31. The current-limit threshold VLMT is utilized to limit a maximum of the switching current IP. Once the current-sense signal VCS exceeds the current-limit threshold VLMT, the comparator 31 will generate a first signal SOC to the PWM circuit 30. The feedback signal VFB and the current-sense signal VCS are respectively supplied to a positive terminal and a negative terminal of the comparator 32. Once the current-sense signal VCS exceeds the feedback signal VFB, the comparator 32 will generate a second signal SRG to the PWM circuit 30. The PWM circuit 30 therefore generates a switching signal SPWM to drive the transistor 20 in response to the first signal SOC and the second signal SRG.
FIG. 2 shows the PWM circuit 30 of the conventional power converter in FIG. 1. The PWM circuit 30 comprises an oscillator 301 (OSC) an inverter 302, a flip-flop 303, an AND gate 304, NAND gates 305 and 306, and a blanking circuit 307 (BNK). An output of the oscillator 301 generates a pulsating signal PLS, which is supplied to a clock input terminal ck of the flip-flop 303 for enabling the switching signal SPWM via the inverter 302. An output terminal Q of the flip-flop 303 is connected to a first input terminal of the AND gate 304. An output of the inverter 302 is connected to a second input terminal of the AND gate 304. An output terminal of the AND gate 304 generates the switching signal SPWM. An input terminal D of the flip-flop 303 is supplied with the supply voltage VCC. The first signal SOC and the second signal SRG are both supplied to input terminals of the NAND gate 305. An output terminal of the NAND gate 305 is connected to a first input terminal of the NAND gate 306. Once the switching signal SPWM received at an input terminal of the blanking circuit 307 becomes logic-high, an output terminal of the blanking circuit 307 will output a short logic-low pulse to a second input terminal of the NAND gate 306. An output terminal of the NAND gate 306 is connected to a reset terminal R of the flip-flop 303 to reset the flip-flop 303.
FIG. 3 shows key waveforms of the conventional power converter in FIG. 1. When the switching signal SPWM is disabled, the transistor 20 will be turned off. The current-sense signal VCS is therefore pulled down to a level of the primary ground reference, which equals to 0 volt. Since the primary winding NP is supplied with the input voltage VIN, the level of the drain voltage VD is substantially equal to that of the input voltage VIN when the transistor 20 is turned off.
When the switching signal SPWM is enabled, the transistor 20 will be turned on. The drain voltage VD is pulled down to a voltage level VD1 and the current-sense signal VCS equals to a voltage level V1. The voltage levels VD1 and V1 can be expressed by:VD1=IP1×(RDSON+R25)  (1)V1=IP1×R25  (2)
Where IP1 is an initial value of the switching current IP flowing through the transistor 20 as the switching signal SPWM is just enabled; R25 is the resistance of the current-sense resistor 25; and RDSON is the on-resistance of the transistor 20.
Meanwhile, the input voltage VIN will start to energize the primary winding NP, which causes the drain voltage VD to ramp up with a first slope. It is noted that the current-sense signal VCS will also ramp up with a second slope which is equal to the first slope.
Whether the current-sense signal VCS exceeds the current-limit threshold VLMT or the feedback signal VFB, the flip-flop 303 (shown in FIG. 2) will be reset and therefore disables the switching signal SPWM. This will accordingly turns off the transistor 20. The drain voltage VD will be pulled up to the level of the input voltage VIN and the current-sense signal VCS will be pulled down to the level of the primary ground reference again.